CL130AL
SilTerra’s CL130AL technology adopts the same front end design rule as industry standard CL130G CMOS Logic technology but integrated with aluminum backend interconnection. The CL130AL provides optimum cost over performance with its marginally smaller SRAM cell density and virtually identical gate power consumption as compared to CL130G.
As compared with industry standard aluminum CL180G CMOS technology, CL130AL offers significant device performance advantages and produces more gross dies in a wafer which is ideal for cost effective mainstream, consumer electronic applications.
SilTerra’s CL130AL technology is supported by ARM based standard cell libraries, high density memory compilers, programmable CUP-style general purpose IO (GPIO) and Ememory’s One-Time-Programming IP.
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| CL130AL Key Process Features |
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Industry standard 0.13µm CMOS logic
front end design |
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Single-poly, up to
six metal layers |
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USG inter-metal dielectric |
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Dual
Gate voltages: 1.2V core, 3.3V I/O |
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Aluminum
metallization |
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Physical Design Rule
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Electrical Design Rule (Specification)
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