CMOS Logic


 
CL180LP

CL180LP (0.18um CMOS Low Power), a foundry matched technology from SilTerra is optimized for low leakage, making it an ideal technology platform for battery power applications. 
 
The technology is supported by a set of silicon proven standard design libraries, SRAM compiler and I/O.

 
 

CL180LP Key Process Features
Single poly, up to six metal layers
Supports 1.8V and 3.3V power supplies
Very low leakage current
Shallow trench isolation
Dual gate oxide
Surface channel NMOS and PMOS
Cobalt silicided source, drain and gate
Borderless contact and via
Aluminum metallization with tungsten plug
High density plasma gap fill
FSG inter-metal dielectrics

 


 

Physical Design Rule

 

 

Electrical Design Rule (Specification)

 




 

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