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Foundry Reference Design Flow

With collaboration with 3rd party EDA tools vendors, SilTerra’s reference design flow provides customers with a proven design methodology to ensure first time design success for rapid time-to- market and high yielding wafer manufacturing. The reference design flow support Mentor, Synopsys and Cadence EDA tools right from RTL coding until GDS generation for tapeout. These EDA tools have been verified and are correlated with SilTerra’s process rules and device specification.

   
 
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