CL180LP

Key Process Features: Supports 1.8V and 3.3V power supplies Very low leakage current Single poly, up to six metal layers Shallow trench isolation Dual gate oxide Surface channel NMOS and PMOS Cobalt silicided source, drain and gate Borderless contact and vias High density plasma gap fill FSG inter-metal dieletric

Key Design Rules:
 

Pitch Active 0.50µm Poly 0.43µm Metal 1 0.46µm Metal 2 - 4 0.56µm Top Metal 0.90µm

Key Performance Parameters:
 

1.8V Thin Gate 3.3V Thick Gate   NMOS PMOS NMOS PMOS VT 0.60V -0.60V 0.72V -0.73V IDsat 500µA/µm 185µA/µm 600µA/µm 300µA/µm RO Delay  36ps 50ps

Please contact us for detailed technical information.