CL180MR

Key Process Features: Supports 1.8V and 3.3V power supplies. Single poly, up to six metal layers Shallow trench isolation Dual gate oxide Surface channel NMOS and PMOS Cobalt silicided source, drain and gate Borderless contact and vias High density plasma gap fill FSG inter-metal dielectric Native transistors MiM capacitor Thick metal spiral inductor Varactor

Key Design Rules:
 

Pitch Active 0.50µm Poly 0.43µm Metal 1 0.46µm Metal 2 - 5 0.56µm Top Metal 0.90µm

Key Performance Parameters:
 

2.5V Thin Gate 3.3V Thick Gate 1.8V Native 3.3V Native   NMOS PMOS NMOS PMOS NMOS PMOS VT 0.42V -0.50V 0.72V -0.74V -0.09V -0.09V IDsat 600µA/µm 260µA/µm 600µA/µm 300µA/µm 425µA/µm 425µA/µm RO Delay 27ps 50ps - -

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