IoT Technology – I11L
I11L Key Process Features
- Ultra low leakage technology
- Single-poly and up to six metal layers
- Dual gate: 1.5V core and 3.3V I/O
- 3 flavours of LV devices (ULL, LP, HP) offered
- Cobalt silicided source, drain and gate
- Shallow trench isolation
- Aluminum metallization with tungsten plug
- FSG inter-metal dielectric
- Metal-Insulator-Metal (MIM) Capacitor (Option)
- Custom made Flash macro configuration
- SRAM bit cell: 1.65µm2
Physical Design Rules
| Parameter | Unit | 1.5V Pitch | 3.3V Pitch |
| Active | μm | 0.325 | 0.325 |
| Poly | μm | 0.28 | 0.514 |
| Contact | μm | 0.306 | 0.306 |
| Metal 1 | μm | 0.316 | 0.316 |
| Via 1 | μm | 0.369 | 0.369 |
| Metal X | μm | 0.37 | 0.37 |
| Via X | μm | 0.369 | 0.369 |
| Via Top | μm | 0.639 | 0.639 |
| Metal Top | μm | 0.738 | 0.738 |
Electrical Design Rules
| 1.5V Core | Parameter | Unit | ULL 10 x 0.13 |
LL 10 x 0.13 |
HP 10 x 0.13 |
| NMOS | VTN_LIN | V | 0.66 | 0.51 | 0.49 |
| DN | μA/μm | 370 | 530 | 590 | |
| IOFFN (typical) | pA/μm | 0.3 | 8 | 25 | |
| PMOS | VTN_LIN | V | 0.68 | 0.57 | 0.55 |
| IDP | μA/μm | 145 | 210 | 230 | |
| IOFFP (typical) | pA/μm | 0.3 | 2.5 | 6 |
Foundation IP
| IP Name | Vendor | Available |
| Std Cell SC6 RVt ULL | VeriSilicon | Now |
| Memory Compilers | VeriSilicon | Now |
| GPIO | VeriSilicon | Now |
| OTP | CFX | Now |
| MTP | ACTT | 2Q21 |
