CP5V
CP5V is offered for single gate 5V device only. CP5V technology is optimized for power management applications which do not require 1.8V LV device. With lesser total masking counts, this technology offers superior performance at competitive cost for designers.
This technology is supported by proven Foundry design kits and PDK.
CP5V Key Process Features
- Single-poly and up to four metal layers
- Single gate: 5.0V device for both core and I/O
- Supports various BJT devices VPNP & VNPN BJT
- Supports Schottky Barrier Diode
- Cobalt silicided source, drain and gate
- Shallow trench isolation
- Aluminum metallization with tungsten plug
- FSG inter-metal dielectric
- Metal-Insulator-Metal (MIM) Capacitor (Option)
- Power Line Metal for high current carrying
Physical Design Rules
| Parameter | Unit | 5.0V Pitch |
| Active | μm | 0.87 |
| Poly | μm | 0.90 (5.5V max) |
| Contact | μm | 0.47 |
| Metal 1 | μm | 0.46 |
| Via 1 | μm | 0.52 |
| Metal X | μm | 0.56 |
| Via X | μm | 0.52 |
| Metal X (as PLM-1) |
μm | 0.74 |
| Via Top | μm | 2.00 |
| PLM (2.3um) | μm | 2.70 |
| PLM (3um) | μm | 4.00 |
| PLM (4um) | μm | 5.00 |
Electrical Design Rules
| Parameter | Unit | 5.0V w DNW | 5.0V w/0 DNW |
| Vtn_lin | V | 0.725 | 0.775 |
| Vtp_lin | V | -0.717 | -0.685 |
| Idsn | μA/μm | 554 | 538 |
| Idsp | μA/μm | -284 | -297 |
| Ioff | |pA/μm| | <20 | <20 |
w: with ; w/o: without Deep Nwell
