IoT Technology – I18L eFlash

I18L eFlash Key Process Features

  • Ultra low leakage technology
  • Single-poly and up to six metal layers
  • Dual gate: 1.8V core and 3.3V I/O
  • 3 flavors of LV devices (ULL, LP, HP) offered
  • Supports SuperFlash embedded NOR flash module
  • Cobalt silicided source, drain and gate
  • Shallow trench isolation
  • Aluminum metallization with tungsten plug
  • USG inter-metal dielectric
  • Metal-Insulator-Metal (MIM) Capacitor (Option)
  • Custom made Flash macro configuration
  • SRAM bit cell: 2.97µm2

Physical Design Rules

Parameter Unit 1.8V Pitch 3.3V Pitch
Active μm 0.50 0.50
Poly μm 0.43 0.59
Contact μm 0.47 0.47
Metal 1 μm 0.46 0.46
Via 1 μm 0.52 0.52
Metal X μm 0.56 0.56
Via X μm 0.52 0.52
Via Top μm 0.71 0.71
Metal Top μm 0.90 0.90

Electrical Design Rules

Parameter Unit 1.8V
Thin
ULL
1.8V
Thin
LL
1.8V
Thin
HP
3.3V
Thick
Vtn_lin V 0.53 0.53 0.42 0.62
Vtp_lin V -0.64 -0.65 -0.48 -0.66
ldsn μA/μm 520 565 600 605
ldsp μA/μm 200 230 260 290
loff pA/μm <1 <20 <500 <100

Foundation IP

IP Name Vendor Available
Std Cell SC7 RVt ULL VeriSilicon Now
Memory Compilers VeriSilicon Now
GPIO VeriSilicon Now
OTP Ememory Now
MTP ACTT Now
Embedded Flash SST 2Q21