CMOS LOGIC – CL160G

CL160G Key Process Features

  • Single-poly and up to six metal layers
  • Dual gate: 1.8V core and 3.3V I/O
  • Cobalt silicided source, drain and gate
  • Shallow trench isolation
  • Super steep retrograde twin well
  • Aluminum metalization with tungsten plug
  • FSG inter-metal dielectric
  • Metal-Insulator-Metal (MIM) Capacitor (Option)
  • Post shrink SRAM bit cell: 3.76µm2

Physical Design Rules

Parameter Unit C18G Pitch C16G Pitch (after shrink)
Active μm 0.50 0.45
Poly μm 0.43 0.387
Contact μm 0.47 0.423
Metal 1 μm 0.46 0.414
Via 1 μm 0.52 0.46
Metal X μm 0.56 0.50
Via X μm 0.52 0.46
Via Top μm 0.71 0.64
Metal Top μm 0.90 0.81

Electrical Design Rules

Parameter Unit 1.8V
Thin
Gate
3.3V
Thick
Gate
Vtn_lin V 0.42 0.70
Vtp_lin V -0.48 -0.69
ldsn μA/μm 600 620
ldsp μA/μm 260 260
loff pA/μm <500 <100

Foundation IP

IP Name Vendor Available
Std Cell SC9 RVt ARM Now
Std Cell SC7 RVt ARM Now
Memory Compilers ARM Now
OTP Ememory Now
MTP ACTT/Synopsys Now