CMOS LOGIC – CL180GH5

CL180GH5 Key Process Features

  • Single-poly and up to six metal layers
  • Dual gate: 1.8V core and 5.0V IO
  • Cobalt silicided source, drain and gate
  • Steep retrograde twin well
  • Shallow trench isolation
  • Aluminum metalization with tungsten plug
  • FSG inter-metal dielectric
  • Metal-Insulator-Metal (MIM) Capacitor (Option)
  • SRAM bit cell: 4.65µm2

Physical Design Rules

Parameter Unit 1.8V Pitch 5V Pitch
Active μm 0.50 0.87
Poly μm 0.43 0.85 (5.5V max)
0.95 (6V max)
Contact μm 0.47 0.47
Metal 1 μm 0.46 0.46
Via 1 μm 0.52 0.52
Metal X μm 0.56 0.56
Via X μm 0.52 0.52
Via Top μm 0.71 0.71
Metal Top μm 0.90 0.90

Electrical Design Rules

Parameter Unit 1.8V Thin Gate 5V Thick Gate
Vtn_lin V 0.42 0.80
Vtp_lin V -0.48 -0.76
ldsn μA/μm 600 560
ldsp μA/μm 260 280
loff pA/μm <500 <20

Foundation IP

IP Name Vendor Available
Std Cell SC9 RVt ARM Now
Std Cell SC7 RVt ARM Now
Memory Compilers ARM Now
OTP Ememory Now
MTP ACTT Now