HUMANIZE TECHNOLOGY & SHAPE
Through collaboration with 3rd party EDA tools vendors, SilTerra’s reference design flow provides customers with a proven design methodology to ensure first-time design success which will in turn shorten the time-to-market and provide high yielding wafer manufacturing for our customers.
SilTerra’s reference design flow support Mentor, Synopsys and Cadence EDA tools from RTL coding to GDS generation for tapeout. These EDA tools have been verified and strongly correlate with SilTerra’s process rules and device specification.
Design IP is an essential part of the System On Chip (SOC) design methodology. SilTerra works with 3rd party Design IP companies to provide Design IPs that are customized to SilTerra’s processes.
The available IPs are shown in the following table :
SilTerra has established a network of highly qualified Design Service companies to provide comprehensive design services that meet the outsourcing needs of our customers. The services provided range from initial system design to layout and physical verification.
SilTerra’s Design Service Partner Network includes the following Design Service companies