SilTerra’s CL110AL technology is a 10% direct optical shrink from CL130AL design. CL110AL offers significant device performance advantages and produces more gross dies in a wafer which is ideal for cost-effective mainstream consumer electronic applications.


SilTerra’s CL110AL technology is supported by ARM based standard cell libraries,high density memory compilers, programmable CUP-style general purpose IO (GPIO) and One-Time-Programming IP & Multiple Time Programming.

CL110AL Key Process Features

  • Derive from industry standard 0.13µm CMOS logic technology with 10% global shrink
  • Single-poly and up to six metal layers
  • Dual voltages: 1.2V core, 3.3V I/O
  • Regular Vt, High Vt and Low Vt device options offered
  • Cobalt silicided source, drain and gate
  • Shallow trench isolation
  • Super steep retrograde twin well
  • Aluminum metalization
  • FSG inter-metal dielectric
  • Metal-Insulator-Metal (MIM) Capacitor (Option)
  • Post shrink SRAM bit cell: 1.92µm2 and 1.65µm2

Physical Design Rules

Parameter Unit C13AL 1.2V Pitch C11AL 1.2V Pitch
Active μm 0.36 0.324
Poly μm 0.31 0.28
Contact μm 0.34 0.306
Metal 1 μm 0.35 0.315
Via 1 μm 0.41 0.369
Metal X μm 0.41 0.369
Via X μm 0.41 0.369
Via Top μm 0.71 0.639
Metal Top μm 0.82 0.738

Electrical Design Rules

Parameter Unit 1.2V RVt 1.2V LVt 3.3V
Vtn_lin V 0.33 0.29 0.58
Vtp_lin V 0.35 0.28 0.62
ldsn μA/μm 535 650 608
ldsp μA/μm 235 300 305
loff nA/μm <2 <50 <0.1

Foundation IP

IP Name Vendor Available
Std Cell SC9 RVt ARM Now
Std Cell SC7 RVt ARM Now
Std Cell SC7 LVt ARM Now
Std Cell SC7 HVt Custom Now
Memory Compilers ARM Now
CUP IO (6LM only) ARM Now
OTP Ememory Now
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