SilTerra’s CL110G is a 10% optical shrink version from generic CL130G process.The electrical performance and design rules of device will remain as CL130G before tapeout but the technology will enable more gross die per wafer which provides a natural cost reduction plan for our customers.

CL110G Key Process Features

  • Derived from industry standard 0.13µm CMOS logic technology with 10% global shrink
  • Single-poly and up to eight metal layers
  • Multiples voltages: 1.2V core, 2.5V/3.3V I/O
  • Regular Vt and Low Vt device options offered
  • Cobalt silicided source, drain and gate
  • Shallow trench isolation
  • Super steep retrograde twin well
  • Dual damascene copper metalization
  • FSG inter-metal dielectric
  • Metal-Insulator-Metal (MIM) Capacitor (Option)
  • Post shrink SRAM bit cell: 1.96µm2 and 1.65µm2

Physical Design Rules

Parameter Unit C13G 1.2V Pitch C11G 1.2V Pitch
Active μm 0.36 0.324
Poly μm 0.31 0.28
Contact μm 0.34 0.306
Metal 1 μm 0.34 0.306
Via 1 μm 0.41 0.369
Metal X μm 0.41 0.369
Via X μm 0.41 0.369
Via Top μm 0.71 0.639
Metal Top μm 0.82 0.738

Electrical Design Rules

Parameter Unit 1.2V RVt 1.2V HVt 2.5V 3.3V
Vtn_lin V 0.33 0.44 0.47 0.58
Vtp_lin V 0.35 0.46 0.50 0.61
ldsn μA/μm 535 417 630 610
ldsp μA/μm 235 170 300 300
loff nA/μm <1 <0.03 <0.03 <0.05

Foundation IP

IP Name Vendor Available
Std Cell SC9 RVt ARM Now
Std Cell SC9 HVt ARM Now
Std Cell SC9 LVt Custom Now
Memory Compilers ARM Now
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