C13AL – 130nm CMOS Logic 1.2V/3.3V Al

CMOS LOGIC – CL130AL

SilTerra’s CL130AL technology adopts the same front end design rule as industry standard CL130G CMOS Logic technology but is integrated with aluminum backend interconnection. The CL130AL provides optimum cost over performance and virtually identical gate power consumption as compared to CL130G.

SilTerra’s CL130AL technology is supported by ARM-based standard cell libraries, One-Time-Programming IP.

CL130AL Key Process Features

Industry standard 0.13µm CMOS front end design
Single-poly and up to six metal layers
Dual voltages: 1.2V core, 3.3V I/O
Cobalt silicided source, drain and gate
Shallow trench isolation
Super steep retrograde twin well
Aluminum metalization
FSG inter-metal dielectric
Metal-Insulator-Metal (MIM) Capacitor (Option)
SRAM bit cell: 2.38µm2

Physical Design Rules

Parameter	Unit	1.2V Pitch	3.3V Pitch
Active	μm	0.36	0.36
Poly	μm	0.31	0.55 (PMOS) 0.60 (NMOS)
Contact	μm	0.34	0.34
Metal 1	μm	0.35	0.35
Via 1	μm	0.41	0.41
Metal X	μm	0.41	0.41
Via X	μm	0.41	0.41
Via Top	μm	0.71	0.71
Metal Top	μm	0.82	0.82

Electrical Design Rules

Parameter	Unit	1.2V RVt	3.3V
Vtn_lin	V	0.33	0.58
Vtp_lin	V	0.35	0.62
ldsn	μA/μm	535	608
ldsp	μA/μm	235	305
loff	nA/μm	<2	<0.1

Foundation IP

IP NameVendorAvailable

Std Cell SC9 RVt	ARM	Now
Std Cell SC7 RVt	ARM	Now
Memory Compilers	ARM	Now
CUP IO (6LM only)	ARM	Now
OTP	Ememory	Now