C13G – 130nm CMOS Logic 1.2V/2.5V, 1.2V/3.3V Cu

CMOS LOGIC – CL130G

SilTerra’s CL130G technology (0.13um CMOS Logic Generic) is process-matched to leading foundries. The all-copper process features borderless contacts and vias and up to eight layers of metal. This technology offers high speed and high gate density performance which is suitable for design in high speed digital consumer, wired communication and computation related applications.

Our CL130HVt technology (0.13um CMOS Logic High Vt) features optimum transistor performance between speed and standby power. This process technology targets high speed portable devices.

Both CL130G and CL130HVt technologies are supported by silicon-verified standard design libraries, SRAM compilers, I.O. Libraries and IPs.

CL130G Key Process Features

Industry standard 0.13µm CMOS logic technology
Single-poly and up to eight metal layers
Multiple voltages: 1.2V core, 2.5V/3.3V I/O
Regular Vt and Low Vt device options offered
Cobalt silicided source, drain and gate
Shallow trench isolation
Super steep retrograde twin well
Dual damascene copper metalization
FSG inter-metal dielectric
Metal-Insulator-Metal (MIM) Capacitor (Option)
SRAM bit cell: 2.43µm2

Physical Design Rules

Parameter	Unit	1.2V Pitch	2.5V Pitch	3.3V Pitch
Active	μm	0.36	0.36	0.36
Poly	μm	0.31	0.53	0.55 (PMOS) 0.60 (NMOS)
Contact	μm	0.34	0.34	0.34
Metal 1	μm	0.34	0.34	0.34
Via 1	μm	0.41	0.41	0.41
Metal X	μm	0.41	0.41	0.41
Via X	μm	0.41	0.41	0.41
Via Top	μm	0.71	0.71	0.71
Metal Top	μm	0.82	0.82	0.82

Electrical Design Rules

Parameter	Unit	1.2V RVt	1.2V HVt	2.5V	3.3V
Vtn_lin	V	0.33	0.44	0.47	0.58
Vtp_lin	V	0.35	0.46	0.50	0.61
ldsn	μA/μm	535	417	630	610
ldsp	μA/μm	235	170	300	300
loff	nA/μm	<1	<0.03	<0.03	<0.05

Foundation IP

IP Name	Vendor	Available
Std Cell SC9 RVt	ARM/Synopsys	Now
Std Cell SC9 HVt	ARM	Now
Std Cell SC9 LVt	Custom	Now
Std Cell SC7 RVt	ARM	Now
GPIO	Synopsys	Now
OTP	Ememory	Now
Memory Compilers	ARM/Synopsys	Now