CMOS LOGIC – CL150G

CL150G Key Process Features

  • Single-poly and up to six metal layers
  • Dual gate: 1.8V core, 3.3V I/O
  • Cobalt silicided source, drain and gate
  • Shallow trench isolation
  • Super steep retrograde twin well
  • Aluminum metalization with tungsten plug
  • FSG inter-metal dielectric
  • Metal-Insulator-Metal (MIM) Capacitor (Option)
  • Post shrink SRAM bit cell: 3.35µm2

Physical Design Rules

ParameterUnitC18G PitchC15G Pitch (after shrink)
Activeμm0.500.42
Polyμm0.430.35
Contactμm0.470.395
Metal 1μm0.460.386
Via 1μm0.520.436
Metal Xμm0.560.47
Via Xμm0.520.436
Via Topμm0.710.596
Metal Topμm0.900.756

Electrical Design Rules

ParameterUnit1.8V
Thin
Gate		3.3V Thick Gate
Vtn_linV0.420.67
Vtp_linV-0.49-0.68
ldsnμA/μm620620
ldspμA/μm270310
loffpA/μm<500<100

Foundation IP

IP Name Vendor Available
Std Cell SC9 RVt ARM Now
Std Cell SC7 RVt ARM Now
Memory Compilers ARM Now
OTP Ememory Now
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