SilTerra’s CL180MR (0.18um RFCMOS) is developed specifically for wireless applications in FM, Zigbee, WLAN , Bluetooth and other RF transceiver and tuners. Many RF circuits and models are already proven in our RFCMOS technology. This technology is supported with complete RF models and RF design kits that are silicon proven.

CL180MR Key Process Features

  • Single-poly and up to six metal layers
  • Dual gate: 1.8V core and 3.3V I/O
  • Cobalt silicided source, drain and gate
  • Shallow trench isolation
  • Aluminum metallization with tungsten plug
  • FSG inter-metal dielectric
  • Metal-Insulator-Metal (MIM) Capacitor ( 1fF/µm2 or 2fF/µm2 )
  • Metal finger capacitor ( 1.30fF/µm2 )
  • Thick metal spiral Inductor (2.3mm)
  • Ft NMOS (53GHz)

Physical Design Rules

Parameter Unit 1.8V Pitch 3.3V Pitch
Active μm 0.50 0.50
Poly μm 0.43 0.59 (NMOS) 0.55 (PMOS)
Contact μm 0.47 0.47
Metal 1 μm 0.46 0.46
Via 1 μm 0.52 0.52
Metal X μm 0.56 0.56
Via X μm 0.52 0.52
Via Top μm 0.71 0.71
Metal Top μm 0.90 0.90

Electrical Design Rules

Parameter Unit 1.8V Thin Gate 3.3V Thick Gate
Vtn_lin V 0.42 0.71
Vtp_lin V -0.48 -0.68
ldsn μA/μm 600 620
ldsp μA/μm 260 300
loff pA/μm <500 <100

Foundation IP

IP Name Vendor Available
Std Cell SC9 RVt ARM Now
Std Cell SC7 RVt ARM Now
Memory Compilers ARM/Sysnopsys Now
OTP Ememory Now
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